The present invention relates to fuse structures on Random Access Memory (RAM), and more particularly to fuse structures with charge protection circuits on Random Access Memory (RAM) devices.
Advances in semiconductor processing technologies, such as high-resolution photolithography and anisotropic plasma etching, are dramatically reducing the feature sizes of semiconductor devices and increasing the device packing density. As the density of the semiconductor devices increases and the number of discrete devices increases on the chip, the final product yield for many integrated circuit devices (chip yield) may decrease as well. For example, as dynamic random access memory (DRAM) in the semiconductor device becomes highly integrated, the size of memory cells on a DRAM chip is reduced. If one of the DRAM memory cells has a defect, which may be caused by random defects generated in the manufacturing process, the DRAM will not function properly and is determined to be defective.
There is, however, high possibility that only a small number of defective memory cells exist in a memory product. If all memory products with defective memory cells are discarded, the yield of final products will be very low. Recently, additional rows of memory cells, i.e. redundant memory cells, have been disposed in a RAM device along with the main memory cells. Fuse circuits are built between row or column decoders and main memory cell arrays, respectively. Upon detection of one or more defective cell(s) in the main memory cell array, the corresponding fuse circuit is broken from the memory cell array with defective memory cells. Conventionally, the fuse layer is formed as an extended part of a polysilicon or metal layer at the same time the conductively doped polysilicon or metal layer is patterned to form part of the semiconductor device, such as the FET gate electrodes or the local interconnects. Currently, lasers are used to routinely open connections, i.e. fuses, in RAM devices, such as in DRAM or SRAM devices, to disable defective rows of memory cells and to modify the address decoder so that spare rows of memory cells are connected instead.